1. Field of the Invention
This invention relates to core memories having cores inductively coupled by balanced conductor pairs alternately carrying large currents and small differential switching signals, and more particularly to such core memories having circuit elements connected to the conductor pairs intermediate the cores of a bit position to limit differential voltages and provide a selectively operable discontinuity for improving sense-inhibit recovery time.
2. History of the Prior Art
A conventional 3D, three wire core memory includes a plurality of rectangular arrays of magnetic cores with each array representing one bit position. A plurality of orthogonal X and Y drive wires are inductively coupled to the cores of the arrays with each X drive conductor inductively coupling one corresponding row from each array and each Y drive conductor inductively coupling one corresponding column from each array. When partial select currents are passed through one Y drive wire and one X drive wire there is a coincidence of the two partial select currents at one core in each bit position with the driving force being sufficient to switch only the selected core at the coincidence points of the X and Y drive currents. A pair of senseinhibit conductors is provided for each bit position and inductively couples the cores thereof in a balanced manner with each sense-inhibit conductor passing through the array parallel to the Y drive line conductors and inductively coupling half of the cores in the bit position. If it is desired not to write a one into a selected core at a given bit position, partial select inhibit currents are driven in parallel through the two sense-inhibit conductors at the given bit position in opposition to the Y drive current, causing the algebraic sum of the currents at the selected core to be less than that required for switching.
The inhibit currents are typically on the order of several hundred milliamps and cause a substantial amount of electrical energy to be stored by the sense-inhibit line pairs. The time required for this energy to dissipate upon termination of an inhibit current is much greater than the 200-400 nanosecond switching time of a core, particularly in applications where the sense-inhibit lines inductively couple at least 8K cores. During a subsequent read cycle, selected X and Y read drive currents, which are opposite in polarity to the write drive currents, drive a selected core at each bit position in a manner tending to switch it in the opposite or read direction back to zero. If a given core already stores a zero before it is driven by coincident read currents very little flux is switched in the core and only a small noise voltage is induced on the inductively coupled sense-inhibit line. However, if a given selected core is in the one state of magnetization a substantial amount of flux is switched to the zero state and an output switching pulse (U1) having a typical peak voltage on the order of 13-40 millivolts is generated differentially across the sense-inhibit line pair. This U1 differential signal may be relatively small compared to the voltages which appear on the sense-inhibit lines as a result of the retained energy which must be dissipated following termination of an inhibit current. In order to minimize the recovery time, the sense-inhibit lines of each pair are connected together at one end and driven in parallel to provide substantially equal inhibit currents. Because of chosen symmetry, differential voltage components between the lines of a pair are smaller and dissipate more rapidly than the common mode voltage components of the signals which remain between the two lines after termination of the inhibit currents. The switching signal can thus be sensed differentially across the unconnected ends of a pair of sense-inhibit lines without waiting for total dissipation of the common mode electrical signals. Reading is typically delayed until the differential signals dissipate to a voltage level of about 5 millivolts which will not interfere with the U1 switching signal.
Because the sense-inhibit line pairs are driven in parallel with substantially identical currents, are threaded through an array in a balanced manner, are substantially equal in length, and are substantially equal in diameter it would be expected that the differential voltages appearing between a pair of sense-inhibit conductors would be quite small. However, because of normal tolerance deviations in the physical characteristics of the wires, normal tolerance variations in the manner of stringing the wires through the cores of the memory, small deviations in drive current magnitudes, and deviations caused by different magnetic memory states of the inductively coupled cores, differential voltages which are substantial with respect to the U1 switching signal do appear on the sense-inhibit line pairs as a result of the inhibit drive currents. At the high frequencies involved in core memory operations the sense-inhibit lines are relatively long with respect to the wavelength of differential voltage signals induced thereon and thus appear as transmission lines. As a result, periodic voltage pulses appear at the sensed terminals with a period tending to equal the propagation time for a voltage pulse to travel from the sensed terminals to the common terminals and back. These reflections can be reduced somewhat by providing transmission line resistive terminations at the sense-inhibit line terminals but cannot be eliminated because of imperfect impedance matching. In a typical 8K memory it takes at least 340 nanoseconds for these reflecting differential voltage pulses to be reduced to the level of 5 millivolts peak-to-peak. During this time interval the memory must stand idle and otherwise usable memory operation time is lost. This delay tends to impose greater restrictions on core memory operating speed than core switching time. As the number of words increases, this recovery time increases faster than the proportional increase in the number of words. As a result, manufacturing economies that result from manufacturing memories with more words per module tend to be more than offset by the slower memory operation which is dictated by this senseinhibit recovery time.